1. Field of the Invention
The present invention generally relates to clock-data recovery.
2. Description of Related Art
Persons of ordinary skill in the art understand terms and basic concepts related to microelectronics that are used in this disclosure, such as “signal,” “clock,” “square wave,” “edge (of clock),” “binary data,” “vertical eye opening,” “binary phase detector,” “loop filter,” “voltage-controlled oscillator,” “ADC (analog-to-digital converter),” “inverter,” “delay-lock loop,” and “clock recovery.” Terms and basic concepts like these are apparent to those of ordinary skill in the art and thus will not be explained in detail here.
A clock-data recovery circuit is a circuit that receives a received signal, which carries a stream of serial binary data, and establishes a recovered clock that is aligned with a timing of the received signal. An exemplary waveform of a prior art clock-data recovery circuit, as observed by using an oscilloscope, is shown in FIG. 1A. The received signal, when observed using an oscilloscope, exhibits an “eye pattern”. The recovered clock is represented as a square wave with a first edge (i.e., rising edge) aligned with a data transition of the received signal (e.g., edges 101, 103, 105, 107, and 109) and a second edge (i.e., falling edge) aligned with a center of the serial binary data carried by the received signal (e.g., edges 102, 104, 106, and 108). Once the recovered clock is properly established, the serial binary data can be detected by sampling the received signal using the second edge of the recovered clock. A principal of clock-data recovery is well known in prior art and thus not described in detail here.
The prior art clock-data recovery circuit works well if the received signal exhibits a symmetrical eye pattern. However, sometimes, the received signal exhibits a nonsymmetrical eye pattern, as shown in FIG. 1B. In such a situation, the second edge 112 will not be perfectly aligned with the optimal sampling instant 113 where the received signal has the maximum “vertical eye opening” when the first edge 111 is aligned with the transition of the data carried by the received signal.
What is desired is a clock-data recovery circuit that establishes a clock with an edge that is aligned with the optimal timing where the received signal has a maximum “vertical eye opening.”